1. Field of the Invention
This invention relates to memory used in computers and other digital systems, and more particularly, to cache memories.
2. Description of the Related Art
Many computers and other digital systems utilize a memory hierarchy in which information (e.g., data, instructions, etc) is stored. Such a memory hierarchy may extend from small, fast memory (e.g., registers), through larger but somewhat slower memory (e.g., random access memory, or RAM), to large and slow memory (e.g., hard disk storage). Using various types of memory in such a hierarchy can allow information to be stored in an appropriate location. For example, registers may be used to store operands and/or results of instructions close to execution time, cache memory may be used to store instructions and/or data that are frequently accessed, RAM may be used to store data and instructions for software programs that are currently active on a computer system, and hard disk storage may be used to store programs and data that are not in use.
In addition to the various levels of memory hierarchy, additional sub-levels may also be present in some systems. For example, a computer system may employ multiple levels of cache memory. A first level cache (L1, or level one cache) may be a memory that is just below a register set in a memory hierarchy. Additional cache levels (e.g. L2, L3 and so forth) may also be present. In some processors, an L0 cache may also be present in the hierarchy between the L1 cache and the registers, wherein the L0 cache is a very small but very fast cache. In general, for a given cache, the average latency of accesses is the same, with the higher level caches having a faster average latency than the lower level caches. For example, the L1 cache may have a first average latency, while the lower level L2 cache may have a second average latency that is slower than that of the L1 cache.
The use of cache memories to store frequently accessed information may improve the performance of a computer system, since accesses to a cache memory may be performed with a latency that is significantly lower than accesses to main memory. Accordingly, larger caches may be implemented in computer systems (including those implemented as part of a processor). However, larger cache memories may consume more circuit area (e.g., such as area on a processor die) that may be needed by other circuits, and may also sacrifice some operating speed, since the latency for accesses to larger memories may be greater than that for smaller memories.